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INTEGRATED CIRCUITS
DATA SHEET
TDA1549T Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
Objective specification File under Integrated Circuits, IC01 August 1994
Philips Semiconductors
Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
FEATURES * Easy application * Finite-duration impulse-response (FIR) filtering and noise shaping incorporated * 2nd-order noise shaper * Wide dynamic range (true 18-bit resolution) * Low total harmonic distortion * No zero-crossing distortion * Superior signal-to-noise ratio * Bitstream continuous calibration conversion concept * Inherently monotonic * Voltage output (1.5 V RMS) at line drive level * Single supply rail (3.8 to 5.5 V) * Optimum output voltage level over the entire supply range * Small outline packaging (SO16) * Wide operating temperature range (-30 to +85 C) * Standard Japanese input format * No analog post-filtering required * Low power consumption * Integrated operational amplifiers. GENERAL DESCRIPTION The TDA1549T (BCC-DAC1) is the first of a new generation of digital-to-analog converters featuring a unique combination of bitstream and continuous calibration concepts. A system of digital filtering, high oversampling, 2nd order noise shaping and continuous calibration digital-to-analog conversion ensures that only simple 1st order analog ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1549T SO16 DESCRIPTION plastic small outline package; 16 leads; body width 7.5 mm
TDA1549T
filtering is required. The circuit accepts 18-bit four times oversampled input data (4fs) in standard Japanese format. Internal FIR filters remove the main spectral components and increase the sampling rate to 96 times (96fs). A 2nd order noise shaper converts this oversampled data to a 5-bit data stream. For low signal levels the converter operates in the 1-bit bitstream mode with attendant high differential linearity. Higher level signals are reproduced using the dynamic continuous calibration technique, thereby guaranteeing high linearity independent of process variations, temperature effects and product ageing. High-precision, low-noise amplifiers convert the digital-to-analog current to an output voltage capable of driving a line output. Externally connected capacitors perform the required 1st order filtering so that no further post-filtering is required. Internal reference circuitry ensures that the output voltage is proportional to the supply voltage, thereby making optimum use of the supply voltage over a wide range (3.8 to 5.5 V). This unique configuration of bitstream and continuous calibration techniques, together with a high degree of analog and digital integration, results in a digital-to-analog conversion system with true 18-bit dynamic range, high linearity and simple low-cost application.
VERSION SOT162-1
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
QUICK REFERENCE DATA SYMBOL VDDD VDDA VDDO IDDD IDDA IDDO Ptot VFS(rms) (THD + N)/S PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage digital supply current analog supply current operational amplifier supply current total power dissipation full-scale output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio note 1 note 1 note 1 note 2 note 2 note 2 note 2 note 3 VDDD = VDDA = VDDO = 5 V at 0 dB signal level at -60 dB signal level at -60 dB signal level; A-weighted S/N tcs BR fBCK TCFS signal-to-noise ratio at bipolar zero current setting time to 1 LSB input bit rate at data input input clock frequency full-scale temperature coefficient at analog outputs (VOL and VOR) operating ambient temperature A-weighted; at code 00000H CONDITIONS MIN. 3.8 3.8 3.8 - - - - - 1.425 - - - - - - 100 - - - - 5.0 5.0 5.0 12 5.5 6.5 120 50 1.500 -90 0.003 -48 0.40 -50 0.38 110 0.1 - - 100 x 10-6 TYP.
TDA1549T
MAX. 5.5 5.5 5.5 18 8 9 185 - 1.575 -83 0.007 -40 1.0 - - - - 9.216 9.216 -
UNIT V V V mA mA mA mW mW V dB % dB % dB % dB s Mbits MHz
Tamb Notes
-30
-
+85
C
1. All VDD and ground pins must be connected externally to the same supply. 2. Measured with VDDD, VDDA and VDDO = 5 V at input data code 00000H. 3. Measured with VDDD, VDDA and VDDO = 3.8 V at input data code 00000H.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
BLOCK DIAGRAM
TDA1549T
Fig.1 Block diagram.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
PINNING SYMBOL WS BCK TEST VOL FILTCL PIN 1 2 3 4 5 DESCRIPTION word select input bit clock input test input; pin should be connected to ground left channel output capacitor for left channel 1st order filter function; should be connected between pins 4 and 5 capacitor for right channel 1st order filter function; should be connected between pins 6 and 7 right channel output internal reference voltage for output channels (12VDD) operational amplifier ground operational amplifier supply voltage analog supply voltage analog ground not connected (this pin should be left open-circuit) digital ground digital supply voltage data input
TDA1549T
FILTCR
6
VOR Vref VSSO VDDO VDDA VSSA n.c. VSSD VDDD DATA
7 8 9 10 11 12 13 14 15 16
Fig.2 Pin configuration.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
FUNCTIONAL DESCRIPTION General The TDA1549T CMOS digital-to-analog bitstream continuous calibration converter incorporates internal digital filtering which increases the oversampling rate of 4fs input data to 96fs, and removes the spectral data components around 4fs, 8fs, and 12fs. A 2nd order noise shaper operating at 96fs outputs a 5-bit data bitstream to the DACs. The filtering required for waveform smoothing and out-of-band noise reduction is achieved by simple 1st order analog post-filtering (see Fig.3). The combination of noise shaping and bitstream continuous calibration digital-to-analog conversion enables high performance and extremely low noise to be achieved. Input The circuit accepts four times oversampled data in 18-bit two's complement standard Japanese format with MSB first. Left and right data channel words are time multiplexed. The input format is illustrated in Fig.5. The bit clock (BCK) operates at 192fs, i.e. 48 times the word select (WS) frequency of 4fs. Oversampling filter The oversampling filter consists of: * A 7th order half-band low-pass FIR filter which increases the oversampling rate from 4 times to 8 times. This removes the spectral components around 4fs and 12fs (see Fig.3). * A linear interpolation section which increases the oversampling rate to 16 times. This removes the spectral components around 8fs. * A sample-and-hold section which provides another 6 times oversampling to 96 times. The zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering removes the spectral components around 16fs. Passband ripple is within 0.1 dB. Stopband attenuation is >50 dB around multiples of the sampling frequency. Noise Shaper
TDA1549T
The 2nd-order digital noise shaper converts the 18-bit data at 96fs into a 5-bit bitstream, while shifting in-band quantization noise to frequencies well above the audio band. For low signal levels the noise shaper output is a 1-bit bitstream. This noise shaping technique used in combination with a special data code and bitstream DAC enables extremely high signal-to-noise ratios to be achieved. Data encoder The data encoder converts the 5-bit two's complement output data from the noise shaper to a 32-bit thermometer code. In traditional unidirectional current converters, half of the full-scale current flows to the output during small signal reproduction. The thermal noise and substrate crosstalk components present in this current severely restrict the dynamic range which can be attained. In this BCC-DAC1 true low-noise performance is achieved using a special data code and bidirectional current sources. The special data code guarantees that only small values of current flow to the output during small-signal passages while larger positive or negative signals are generated using the bidirectional current sources. For every change in the 18-bit input sample only one current source or current sink is switched on. This intrinsically monotonic thermometer code ensures the high differential linearity, zero crossover distortion and superior signal-to-noise ratio associated with bitstream conversion.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
Continuous calibration DAC The stereo 5-bit DAC uses the dynamic continuous calibration technique. The DAC currents (16 sources and 16 sinks) of each channel are repeatedly generated from one single reference current. This duplication is based on an internal charge storage principle and has an inherently high accuracy which is insensitive to ageing, temperature and process variations. Figure 4 shows one such current calibration source. During calibration the cell is connected to the reference current sink Iref via switch S2. The calibration transistor M1 is connected as an MOS diode via the switch S1 forcing its gate potential to assume a value so that the total current of the calibration cell is equal to the reference current. After calibration the gate of M1 is allowed to float. The gate capacitance Cgs retains its potential and the current through the cell remains exactly equal to the reference current. This current is now connected to the output. Each digital-to-analog current source and each current sink is calibrated precisely in this way. Operational amplifiers
TDA1549T
High precision, low-noise amplifiers together with the internal conversion resistors RCONV1 and RCONV2 convert the DAC output current to a voltage capable of driving a line output. This voltage is available at VOL and VOR (1.5 V RMS typical). Connecting external capacitors CEXT1 and CEXT2 between FILTCL and VOL and FILTCR and VOR respectively, provides the required 1st-order post-filtering for the left and right channels (see Fig.1). The combinations of RCONV1 with CEXT1 and RCONV2 with CEXT2 determine the 1st order fall-off frequencies. Internal reference circuitry Internal reference circuitry ensures that the output voltage signal is proportional to the supply voltage, thereby maintaining maximum dynamic range for supply voltages from 3.8 to 5.5 V and making the circuit also suitable for battery-powered applications.
Fig.3 Filter and noise shaper characteristics.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
TDA1549T
(a) calibration. (b) operation.
Fig.4 Calibration principle.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VDDO Txtal Tstg Tamb Ves PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1500 . 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 . THERMAL CHARACTERISTICS SYMBOL Rth j-a HANDLING PARAMETER thermal resistance from junction to ambient in free air VALUE 110 CONDITIONS - - - - -65 -30 -2000 -200 MIN.
TDA1549T
MAX. 7.0 7.0 7.0 +150 +150 +85 +2000 +200 V V V
UNIT
C C C V V
UNIT K/W
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. QUALITY SPECIFICATION Quality specification in accordance with "SNW-FQ-611" is applicable.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDDD VDDA VDDO IDDD IDDA IDDO Ptot RR digital supply voltage analog supply voltage operational amplifier supply voltage digital supply current analog supply current operational amplifier supply current total power dissipation ripple rejection note 1 note 1 note 1 note 2 note 2 note 2 note 2 note 3 note 4 Digital inputs; pins WS, BCK and DATA VIH VIL |ILIH| |ILIL| CI HIGH level input voltage LOW level input voltage HIGH level input leakage current LOW level input leakage current input capacitance VIH = VDDD = 5 V VIH = VSSD = 0 V 0.7VDD - -0.5 - - - - - - - 3.8 3.8 3.8 - - - - - - 5.0 5.0 5.0 12 5.5 6.5 120 50 25 PARAMETER CONDITIONS MIN. TYP.
TDA1549T
MAX.
UNIT
5.5 5.5 5.5 18 8 9 185 - -
V V V mA mA mA mW mW dB
VDD + 0.5 V 0.3VDD 10 10 10 V A A pF
Timing (see Fig.6) OPERATING FREQUENCY fBCK fWS fBCK BR fWS tr tf Tcy tH tL tsu th thWS tsuWS PBR SBA bit clock frequency word select frequency - - - - - - - 108 22 22 32 2 2 32 - 50 192fs fBCK/48 - - - - - - - - - - - - - - 9.216 9.216 192 32 32 - - - - - - - - - Hz Hz
INPUT FREQUENCY clock frequency bit rate data input word select input frequency rise time fall time bit clock cycle time bit clock HIGH time bit clock LOW time data set-up time data hold time word select hold time word select set-up time MHz MHz kHz ns ns ns ns ns ns ns ns ns
Filter characteristics (see Fig.3) pass-band ripple stop-band attenuation < 20 kHz note 5 0.1 - dB dB
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
SYMBOL Reference values Vref RCONV reference voltage level current-to-voltage conversion resistance 2.45 1.6 2.5 2.2 PARAMETER CONDITIONS MIN. TYP.
TDA1549T
MAX.
UNIT
2.55 2.8
V k
Analog outputs; pins VOL and VOR RES VFS(rms) VOFF TCFS resolution full-scale output voltage (RMS value) output voltage DC offset with respect to reference voltage level Vref full-scale temperature coefficient at 0 dB input level; note 6 at -60 dB input level; note 7 at -60 dB input level; A-weighted; note 8 at 0 dB input level; 20 Hz to 20 kHz; note 9 S/N tcs cs |VO| |ZO| RL CL Notes 1. All VDD and VSS pins must be connected externally to the same supply. 2. Measured with VDDD = VDDA = VDDO = 5 V at input data code 00000H. 3. Measured with VDDD = VDDA = VDDO = 3.8 V at input data code 00000H. 4. Vripple = 1% of the supply voltage and fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the external capacitor (CEXT3 in Fig.1) connected to Vref. The value quoted here assumes CEXT3 = 1 F. 5. Around multiples of 4fs. 6. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 192 kHz. (THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz. 7. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 192 kHz. (THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz. 8. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 192 kHz. (THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz and filtered with A-weighted characteristic. 9. Measured with a 0 dB, 18-bit sine wave from 20 Hz to 20 kHz generated at a sampling rate of 192 kHz. (THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz. August 1994 11 signal-to-noise ratio at bipolar zero current setting time to 1 LSB channel separation unbalance between outputs dynamic output impedance output load resistance output load capacitance A-weighted; at code 00000H - 1.425 -80 - - - - - - - - - 100 - 85 - - 3 - - 1.5 -65 18 1.575 -50 bit V mV
100 x 10-6 - -90 0.003 -48 0.40 -50 0.32 -90 0.003 110 0.1 100 0.2 10 - - -83 0.007 -40 1.0 - - -83 0.007 - - - 0.3 - - 200 dB % dB % dB % dB % dB ms dB dB W k pF
(THD + N)/S total harmonic distortion plus noise-to-signal ratio
Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
TDA1549T
Fig.5 Format of input signals.
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Fig.6 Timing of input signals.
Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
APPLICATION INFORMATION
TDA1549T
A typical application diagram is illustrated in Fig.7. The left and right channel outputs can drive a line output directly.
(1) C = 100 nF (chip capacitor).
Fig.7 Application diagram.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
TDA1549T
(1) Level = -60 dB. (2) Level = 0 dB.
Fig.8 Total harmonic distortion plus noise-to-signal ratio as a function of signal frequency.
In Fig.8 measurements were taken with an 18-bit sine wave generated at a sample rate of 192 kHz. The (THD + N)/S was measured over a bandwidth of 20 Hz to 20 kHz. The graph was constructed from average measurement values of a small amount of engineering samples. No guarantee for typical values is implied.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
TDA1549T
Fig.9 Total harmonic distortion plus noise-to-signal ratio as a function of signal level; (A-weighted).
In Fig.9 measurements were taken with an 18-bit sine wave generated at a sample rate of 192 kHz. The (THD + N)/S was measured over a bandwidth of 20 Hz to 20 kHz and filtered with A-weighted characteristic. The graph was constructed from average measurement values of a small amount of engineering samples. No guarantee for typical values is implied.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
PACKAGE OUTLINE
TDA1549T
handbook, full pagewidth
10.5 10.1
7.6 7.4 A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
16
9 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 1.1 0.5 detail A
2.65 2.35
pin 1 index 1 8 0 to 8
o
MBC233 - 1
1.27
0.49 0.36
0.25 M (16x)
Dimensions in mm.
Fig.10 Plastic small outline package; 16 leads; body width 7.5 mm; (SO16; SOT162-1).
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
SOLDERING Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1549T
Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC (BCC-DAC1)
NOTES
TDA1549T
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Philips Semiconductors
Objective specification
Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC
NOTES
TDA1549T
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For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD34 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
Philips Semiconductors

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